The present disclosure generally relates to the field of semiconductors, and more particularly relates to vertical field-effect-transistors.
Vertical transistors are a promising option for technology scaling for 5 nm CMOS technology and beyond. Vertical field-effect-transistors (FETs) mainly comprise a bottom S/D, a vertical fin or nanowire channel, a top S/D, gate contact, and metal contacts to top and bottom S/D. Additional area is consumed in order to make contact to the bottom S/D so that the bottom S/D can be electrically accessed from the top resulting in increased device footprint and reduced device packing density.